Answer to Question #327416 in Assembler for kenzie

Question

Consider the following emission delays for the circuit in Figure 4.24 , page 271 of the book computer organization and design by david patterson.

a) Calculate the maximum time required to execute the LW, SLT, J, BEQ, ADDI and AND commands.

b) What is the critical path of this processor?

c) What is the maximum frequency of this processor?

nstr. memory read/write: 1.2ns

Data memory read/write: 1.4ns

Register file read/write: 0.5ns

Any ALU operation: 0.5ns

Any 2 to 1 mux: 0.1ns

Any adder (except ALU adder): 0.4ns

Answer 1

It's been a while since this question is posted here. Still, the answer hasn't been got. Consider converting this question to a fully qualified assignment, and we will try to assist. Please click the link below to proceed: Submit order