Answer to Question #143580 in Assembler for Promise Omiponle

Question

Explain what the Cortex-M0+ “interrupt priority levels” are and how they are used.

Answer 1

“Interrupt priority level” Cortex-M0+ means the numeric value of the interrupt priority. "Urgency" refers to the ability of an interrupt to supersede other interrupts.

Cortex-M uses a “reverse” priority numbering scheme for interrupts. Priority zero corresponds to the interrupt with the highest urgency, and higher numerical priority values correspond to lower urgency

In a nested interrupt system such as on ARM Cortex-M, a ‘more urgent’ interrupt can interrupt a ‘less urgent’ interrupt.

The priority of the exception/interrupt is assigned with an 8-bit priority register, and the number of bits implemented is up to the vendor implementation.

ARM specifies a minimum of 2 bits for the M0/M0+ (supports 4 priority levels for interrupts).