Answer to Question #159412 in Assembler for xherry

Question

a) Suppose a computer having 5 GHz processor with cycle time of 2ns and main memory access time

100ns with CPI is 2 cycle.

i. Calculate the processor performance without cache.

ii. Calculate the performance with L1 cache, assume L1 hit rate is 75% and access time is 1ns.

iii. Calculate the performance with L2 cache, assume L2 hit rate is 90% and access time is 5ns.

iv. Calculate the performance with L3 cache, assume L3 hit rate is 95% and access time is 7ns.

c) It is desired to have memory of 64Kbytes given that a 13 bit address bus is used to address 

memory location. Design the decoding architecture in order to access complete 64Kbytes 

memory also calculates address ranges for each memory chip.

Answer 1

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