Answer to Question #299581 in Assembler for Ime

Question

Let we have a direct mapped cache having four blocks, you are now required to fill the cache blocks against the following address reference. 2,5,8,7,6,5,1,12,22,12

1.      After processing the address reference 6 cache block 0,1,2 and 3 would contain the address reference _________

2.      After processing the address reference 1 cache block 0,1,2 and 3 would contain the address reference _________

3.      The appearance of the address reference 7 in the above mentioned sequence would be a hit/miss

4.      At the end cache block 0,1,2 and 3 would contain the address reference ______

5.      After processing the address reference 7 cache block 0,1,2 and 3 would contain the address reference _________

6.      The second appearance of the address reference 5 in the above mentioned sequence would be a hit/miss

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Answer 1

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